Key Skills: Physical Design Engineer , Floor plan, Power Plan, Timing closure, Physical verification, STA, Static timing Analysis

* Experience in 2-3 full chip project for PD from RTL to GDSII
* ASIC/SoC with First Time Silicon success
* Synthesis, Floorplan, Powerplan, PnR, CTS, Timing closure, Physical verification (DRC/LVS), Chip closure, Low Power

Job Description

Digital circuit design knowledge

Experience in Verilog/VHDL is desirable

Very good Experience in defining/understanding/analysis of module and SoC level design constraints

Very good Experience in Floor plan, Power Plan, Timing closure, Physical verification

Block level experience with 1-2Million gate count design complexity

Experience in low power/multi-power domain/multi-voltage designs

Should have handled the chip closure activities related to foundry and assembly

At least 3-4 full chip tape out experience; multiple foundry experience is an added advantage

Experience in the latest technology nodes like 32/45/65/90

Synthesis and STA is nice to have

Hands on in Synopsys/Mentor/Cadence PD Tools

Perl and Unix

Scripting and automation