Key Skills: Physical Design , synthesis , floor planning, place and route, Clock Tree Synthesis , Power planning & analysis

Skills:

Should have very good conceptual understanding of the technology, design flow and implementation. Should have worked on all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Power planning & analysis (PNS/PNA), Timing/congestion driven & MCMM P&R, Basic PT-SI, Hercules/Calibre Physical verifications, Timing/Xtalk ECO, FV,Familiar with 45/40/28 nm DSM effects, Able to work on the project independently

f. Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues

Tools / Flows: Expertise in ICC Tools is a must

Job Description

Physical Design

a. Expertise in implementation TOP LEVEL / COMPLEX BLOCK LEVEL of multimillion gate SoC designs

b. Technology: 45nm / 65nm / 90nm Technologies

c. Design Complexity: Greater than 1Mn and up to 40Mn Gates

d. Tools / Flows: Expertise in ICC Tools is a must, Scripting using TCL / Perl Desirable

e. Skills: Should have very good conceptual understanding of the technology, design flow and implementation. Should have worked on all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Power planning & analysis (PNS/PNA), Timing/congestion driven & MCMM P&R, Basic PT-SI, Hercules/Calibre Physical verifications, Timing/Xtalk ECO, FV,Familiar with 45/40/28 nm DSM effects, Able to work on the project independently

f. Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues

g. Experience level : 3 6 years

h. Location Bangalore & Hyderabad, Malaysia

i. Education : BE, BS, MS, ME Electronics, Computer Science